In a conventional technique, in order to achieve the low threshold voltage in both an n-type MOS transistor and a p-type MOS transistor of a CMOS (Complementary Metal Oxide Semiconductor) transistor, a so-called dual gate structure in which the gate electrodes are formed of materials having different work functions (Fermi potential in the case of polysilicon) has been employed. More specifically, an n-type impurity and a p-type impurity are implanted into polysilicon films which form the gate electrodes of an n-type MOS transistor and a p-type MOS transistor so as to approximate the work function (Fermi potential) of a gate electrode material of the n-type MOS transistor to the conduction band of silicon and to approximate the work function (Fermi potential) of a gate electrode material of the p-type MOS transistor to the valence band of silicon, thereby reducing the threshold values.
However, in recent years, the thickness of a gate insulating film has become smaller along with the scaling down of a CMOS transistor, and the depletion of a gate electrode when a polysilicon film is used for a gate electrode has become non-negligible. More specifically, an electrical equivalent silicon oxide thickness of the gate insulating film made of a silicon oxide film or the like must be set to about 2 nm or smaller due to the scaling down. However, in this case, a parasitic capacity generated in the gate electrode by the depletion of the gate electrode becomes so large that cannot be neglected. For this reason, the use of a metal film as a gate electrode material instead of a polysilicon film has been examined (for example, Japanese Patent Application Laid-Open No. 2002-118175).